Programmable integrated circuits (ICs) are often used to implement digital logic operations according to user configurable input. Example programmable ICs include complex programmable logic devices (CPLDs) and field programmable gate arrays (FPGAs). CPLDs often include several function blocks that are based on a programmable logic array (PLA) architecture with sum-of-products logic. A configurable interconnect matrix transmits signals between the function blocks.
An example FPGA includes an array of configurable logic blocks (CLBs) and a ring or columns of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure (routing resources). The CLBs, IOBs, and interconnect structure are typically programmed by loading configuration data (“configuration bitstream”) into internal configuration memory cells. The state of the configuration memory cells determines the function of the CLBs, IOBs, and interconnect structure. The configuration bitstream may be read from an external memory, such as an EEPROM, EPROM, PROM, and the like, though other types of memory may be used.
A conventional design process begins with the creation of the design. The design specifies the function of a circuit at a schematic or logic level and may be represented using various hardware description languages (e.g., VHDL, ABEL, or Verilog) or schematic capture programs. The design is synthesized to produce a logical network list (“netlist”), and the synthesized design is mapped onto primitive components within the target device (e.g., programmable logic blocks of an FPGA).
Following mapping, placement of the components of the synthesized and mapped design is performed for the target device. During placement, each mapped component of the design is assigned to a physical position on the device. The placer attempts to place connected design objects in close physical proximity to one another in order to conserve space and increase the probability that the required interconnections between components will be successfully completed by the router. Placing connected components close to one another also generally improves the performance of the circuit since long interconnect paths are associated with excess capacitance and resistance, resulting in longer delays and greater power consumption.
Specified connections between components of the design are routed within the target device for the placed components. The routing process specifies physical wiring resources that will be used to conduct signals between pins of placed components of the design. For each connection specified in the design, the routing process allocates wire resources necessary to complete the connection. As used herein, the selection and assignment of wire resources in connecting the output pin of one component to the input pin of another component is referred to as routing a net. When nets have been routed using most or all of the wiring resources in a given area, the area is generally referred to as congested, which creates competition for the remaining wiring resources in the area or makes routing of additional nets in the area impossible.
To expedite development, a number of sub-circuits of a system may be developed in parallel by respective teams of developers. However, without proper coordination, placement and routing of all of the sub-circuits on the target programmable IC may not be possible. For example, the target programmable IC may not have sufficient resources to place all of the sub-circuits together on the programmable IC. Similarly, assuming placement can be achieved, there may be insufficient routing resources to interconnect the placed components as required.
In order to ensure that sufficient resources will be available to implement the sub-circuits of a design, each development team may be assigned a respective region of programmable fabric of a programmable IC. By restricting circuit development of each team to a different region, placement conflicts between the teams may be avoided. Further, because the assigned regions are mutually exclusive, placement and routing may be performed for each region individually during development. This allows a development team to test and optimize the sub-circuit under development with the expectation that the placement and routing within the assigned region will be maintained in the complete design.
However, for programmable ICs such as FPGAs, all hardware resources needed to implement a sub-circuit may not be available in the assigned region. For example, some resources of a programmable IC such as global clock sources (e.g., BUFGs, MMCMs, PLLs), reset, PCI, Serdes circuits, JTAG, BSCAN, DNA_PORT, DCI, EFUSE, etc., are utilized by many or all sub-circuits but may be outside the assigned region. For ease of reference, resources shared by multiple regions may be referred to as global resources. To enable parallel development of sub-circuits the global resources must be located outside of the assigned regions. Routing between the assigned regions and global resources poses a significant challenge for many development flows.
In one approach, respective routing resources are explicitly assigned to a team to route signals between each assigned region and required global resources. FIG. 1 shows a programmable IC design layout with assigned routing channels reserved to provide routing between assigned placement regions and global resources. In this example, four regions (112, 114, 116, and 118) are defined in programmable resources 106 of the programmable IC 102. Each sub-circuit to be implemented in the regions requires use of global resources 104 and 108. In order to ensure that routing can be performed when independently developed sub-circuits of the four regions are combined into the completed circuit, routing resources are reserved to form routing channels. For example, region 112 has one routing channel 140 reserved to route signals between region 112 and global resources 104. As another example, region 118 has one routing channel 142 reserved to route signals between region 118 and global resources 104 and a second routing channel 144 reserved to route signals between region 118 and global resources 108. The routing channels are mutually exclusive to allow each team to perform routing of signals with routing resources in the channels. As a result, the routing channels cannot cross. This may significantly restrict versatility of circuit designs. For example, signals from region 116 may not be routable to pin 130 of global resources 108 because routing paths are blocked by routing channels 144 of region 118.
One or more embodiments may address one or more of the above issues.